A new structure to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate

ABSTRACT

A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly- 1  layer to form a vertical control gate followed by depositing a poly- 2  layer to form a spacer floating gate adjacent to the control gate with an intervening intergate oxide layer. The source is self-aligned and the floating gate is also formed to be self-aligned to the control gate, thus making it possible to reduce the cell size. The resulting self-aligned source alleviates punch-through from source to control gate while the self-aligned floating gate with respect to the control gate provides improved programmability. The method also replaces the conventional poly oxidation process thereby yielding improved sharp peak of floating gate for improved erasing and writing of the split-gate flash memory cell.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The present invention relates to semiconductor memory devices andmore particularly to a method of forming a split-gate flash memory cellhaving a self-aligned source as well as a floating gate self-aligned toa control gate.

[0003] (2) Description of the Related Art

[0004] A split-gate flash memory device is characterized by itssplit-gate side (between the control gate and the drain) and thestacked-side (between the floating gate and the source). Conventionally,the floating gate is not self-aligned to the control gate, and neitheris the self-aligned source commonly used. Without self-aligned source,the problem of punch-through from the source to the control gate isencountered which in turn causes programming fails. And in the absenceof alignment between the floating gate and the control gate, themisalignment causes variability of the coupling ratio, which also causesweak programmability in the cell. As is known, the coupling ratioaffects the program speed, that is, the larger the coupling ratio, thefaster is the programming speed, and is not a fixed value by virtue ofthe variability of the channel length and hence that of the overlapbetween the floating gate and the source. Usually, if channel length isincreased through greater lateral diffusion in the source region,punchthrough occurs due to excessive current well below the thresholdvoltage. It is disclosed later in the embodiments of this invention thatthese problems can be alleviated by forming self-aligned source and alsoself-aligned floating gate with respect to the control gate. As an addedadvantage, it is shown that the cell size can be reduced by usingself-alignment methods and self-aligned structures of this invention.

[0005] Over the years, numerous improvements in the performance as wellas in the size of memory devices have been made by varying the simple,basic one-transistor memory cell, which contains one transistor and onecapacitor. The variations consist of different methods of formingcapacitors, with single, double or triple layers of polysilicon, anddifferent materials for the word and bit lines. In general, memorydevices include electrically erasable and electrically programmableread-only memories (EEPROMs) of flash electrically erasable andelectrically programmable read-only memories (flash EEPROMs). Many typesof memory cells for EEPROMs or flash EEPROMs may have source and drainsregions that are aligned to a floating gate or aligned to spacers. Whenthe source and drain regions are aligned to the floating gate, a gateelectrode for a select transistor is separate from the control gateelectrode of the floating gate transistor. Separate select and controlgates increase the size of the memory cell. If the source and drainregions are aligned to a spacer formed after the floating gate isformed, the floating gate typically does not overlie portions of thesource and drain regions. Programming and erasing performance isdegraded by the offset between the floating gate and source and drainregions.

[0006] Most conventional flash-EEPROM cells use a double-polysilicon(poly) structure of which the well known split-gate cell is shown inFIG. 1a. Here, two MOS transistors share a source (25). Each transistoris formed on a semiconductor substrate (10) having a first doped region(20), a second doped region (25), a channel region (23), a gate oxide(30), a floating gate (40), intergate dielectric layer (50) and controlgate (60). Substrate (10) and channel region (23) have a firstconductivity type, and the first (20) and second (25) doped regions havea second conductivity type that is opposite the first conductivity type.

[0007] As seen in FIG. 1a, the first doped region, (20), lies within thesubstrate. The second doped region, (25), also lies within substrate(10) and is spaced apart form the first doped region (20). Channelregion (23) lies within substrate (10) and between first (20) and second(25) doped regions. Gate oxide layer (30) overlies substrate (10).Floating gate (40), to which there is no direct electrical connection,and which overlies substrate (10), is separated from substrate (10) by athin layer of gate oxide (30) while control gate (60), to which there isdirect electrical connection, is generally positioned over the floatinggate with intergate oxide (50) therebetween.

[0008] In the structure shown in FIG. 1a, control gate (60) overlaps thechannel region, (23) under the floating gate, (40). This structure isneeded because when the cell is erased, it leaves a positive charge onthe floating gate. As a result, the channel under the floating gatebecomes inverted. The series MOS transistor (formed by the control gateover the channel region) is needed in order to prevent current flow fromcontrol gate to floating gate. The length of the transistor, that is theoverlap of the control gate over the channel region (23) determines thecell performance. Furthermore, edges (41), (43) can affect theprogramming of the cell by the source size and hot electron injectionthrough the intergate dielectric layer (50) at such edges. Hot electroninjection is further affected by, what is called, gate bird's beak (43)that is formed in conventional cells. On the other hand, it will beknown to those skilled in the art that corners such as (41) can affectthe source coupling ratio also.

[0009] To program the transistor shown in FIG. 1a, charge is transferredfrom substrate (10) through gate oxide (30) and is stored on floatinggate (40) of the transistor. The amount of charge is set to one of twolevels to indicate whether the cell has been programmed “on” of “off.”“Reading” of the cell's state is accomplished by applying appropriatevoltages to the cell source (25) and drain (20), and to control gate(60), and then sensing the amount of charge on floating gate (40). Toerase the contents of the cell, the programming process is reversed,namely, charges are removed from the floating gate by transferring themback to the substrate through the gate oxide.

[0010] This programming and erasing of an EEPROM is accomplishedelectrically and in-circuit by using Fowler-Nordheim tunneling as iswell known in prior art. Basically, a sufficiently high voltage isapplied to the control gate and drain while the source is grounded tocreate a flow of electrons in the channel region in the substrate. Someof these electrons gain enough energy to transfer from the substrate tothe floating gate through the thin gate oxide layer by means ofFowler-Nordheim tunneling. The tunneling is achieved by raising thevoltage level on the control gate to a sufficiently high value of about12 volts. As the electronic charge builds up on the floating gate, theelectric field is reduced, which reduces the electron flow. When,finally, the high voltage is removed, the floating gate remains chargedto a value larger than the threshold voltage of a logic high that wouldturn it on. Thus, even when a logic high is applied to the control gate,the EEPROM remains off. Since tunneling process is reversible, thefloating gate can be erased by grounding the control gate and raisingthe drain voltage, thereby causing the stored charge on the floatinggate to flow back to the substrate.

[0011] In the conventional memory cell shown in FIG. 1a, word lines (notshown) are connected to control gate (60) of the MOS transistor, whilethe length of the MOS transistor itself is defined by the source (25)drain (20) n+ regions shown in the same Figure. As is well known bythose skilled in the art, the transistor channel is defined by maskingthe n+ regions. However, the channel length of the transistor variesdepending upon the alignment of the floating gate (40) with the sourceand drain regions. This introduces significant variations in cellperformance from die to die and from wafer to wafer. Furthermore, theuncertainty in the final position of the n+ regions causes variations inthe series resistance of the bit lines connected to those regions, andhence additional variation in the cell performance.

[0012] In prior art, Hsia, et al., of U.S. Pat. No. 4,861,730 teach aprocess for producing a high density split gate nonvolatile memory cellwhich includes a floating gate and a control gate that is formed abovethe floating gate. The drain region is self-aligned to the floating gateand source region is self-aligned to the control gate. In U.S. Pat. No.5,063,172, Manley discloses an integrated circuit fabrication methodthat utilizes a conductive spacer to define the gate length of theseries select transistor in a split-gate memory cell, therebyeliminating misalignment problems.

[0013] On the other hand, Chen, et al., in U.S. Pat. No. 5,824,484disclose a sidewall select gate which is formed in conjunction with asemiconductor doped oxide to form a nonvolatile memory cell. In anotherU.S. Pat. No. 5,750,427 Kaya, et al., disclose a non-volatile split-gatememory cell which can be programmed with only a five volt power supplyand is fabricated using standard transistor processing methods. Also, amethod to improve erase speed of split-gate flash is taught by Hsieh, etal., in U.S. Pat. No. 5,858,840 by judiciously implanting nitrogen ionsin the first polysilicon layer and then removing them from the areawhere the floating gate is to be formed.

[0014] While prior art offers different approaches for forming differentsplit-gate flash memory cells, the present invention discloses a stilldifferent method where the floating gate is aligned to the control gate.In the split-gate cells shown in FIG. 1 of prior art, floating gate (40)is not aligned to control gate (60) for the dimensions (x) and (y) aredifferent. This is also shown in a top view given in FIG. 1b. It isdisclosed later in the embodiments of this invention, where thisvariability is avoided and the performance of the split-gate flashmemory cell is improved.

SUMMARY OF THE INVENTION

[0015] It is therefore an object of this invention to provide a methodof forming split-gate flash memory with self-aligned source.

[0016] It is another object of this invention to provide a method offorming split-gate flash memory with self-aligned floating gate tocontrol gate.

[0017] It is yet another object of the present invention to provide asplit-gate flash memory cell with both self-aligned source as well asself-aligned floating gate to control gate in order to alleviatepunch-through from source to control gate as well as to improveprogrammability of the cell.

[0018] These objects are accomplished by providing a silicon substratehaving a plurality of active and field regions defined by shallow trenchisolation (STI); forming first gate oxide layer over said substrate;forming first polysilicon (poly-1) layer over said first gate oxidelayer; forming silicide layer over said poly-1 layer; forming tetraethylorthosilicate (TEOS) layer over said silicide layer; forming firstphotoresist layer over said TEOS layer; patterning said firstphotoresist layer to define control gate area; etching said TEOS layerthrough said patterning in said first photoresist layer and formingopening in said TEOS layer exposing portion of said poly-1 layer;etching said exposed portion of said poly-1 layer and forming controlgate; removing said first photoresist layer; forming second gate oxidelayer over said substrate; forming partial-depth second polysilicon(poly-2) layer over said second gate oxide layer; etching saidpartial-depth poly-2 layer to form drain spacer and source spacer andsharp peak therein; forming second photoresist layer over said substrateto define self-align source (SAS) region; etching partially said secondgate oxide layer through said second photoresist layer in said SASregion; removing said second photoresist layer; forming thirdphotoresist layer over said substrate with openings exposing said poly-2drain spacer and said poly-2 covering said STI regions; etching throughsaid openings in said third photoresist layer to remove said poly-2drain spacer and said poly-2 covering said STI regions to form floatinggate cell; forming fourth photoresist layer over said substrate toredefine self-align source (SAS) region; etching completely said secondgate oxide layer through said fourth photoresist layer until saidsilicon substrate is reached in said SAS region; ion implanting said SASregion; removing said fourth photoresist layer; annealing said tungstensilicide layer; forming drain in said substrate; forming interleveldielectric layer (ILD) over said substrate; and forming metal contact insaid ILD layer to complete the forming of said split-gate flash memorycell.

[0019] These objects are further accomplished by providing memory cellcomprising a substrate having active and field regions defined; a gateoxide formed over said substrate; a poly-1 layer forming a columnarcontrol gate over said gate oxide; a silicide layer covering saidcolumnar control gate; a TEOS layer covering said silicide layer; apoly-2 layer forming a spacer floating gate adjacent and self-aligned tosaid columnar control gate with an intervening intergate oxide layer; asharp poly-2 peak in said spacer floating gate; and a self-alignedsource in said split-gate flash memory cell.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1a shows a cross-sectional view of a split-gate type memorycell of prior art.

[0021]FIG. 1b shows a top view of the split-gate memory cell of priorart of FIG. 1a.

[0022]FIGS. 2a-2 h show plan view of a semiconductor substrate atdifferent stages of the disclosed processing steps. FIGS. 3a-3 h, on theother hand, show cross-sectional views of the substrate corresponding tolocations shown on FIGS. 2a-2 h. FIGS. 3a-3 h will now be described morefully as follows:

[0023]FIG. 3a is a cross-sectional view of the semiconductor substrateof FIG. 2a showing the forming of the passive and active regionsaccording to this invention.

[0024]FIG. 3b is a cross-sectional view of the semiconductor substrateof FIG. 2b showing the forming of the vertical control gate of thisinvention underlying the silicide and TEOS layers according to thisinvention.

[0025]FIG. 3c is a cross-sectional view of the semiconductor substrateof FIG. 2c showing the forming of the spacer floating gate self-alignedto the control gate of this invention.

[0026]FIG. 3d is a cross-sectional view of the semiconductor substrateof FIG. 2d showing the forming of the self-aligned source (SAS) of tothis invention.

[0027]FIG. 3e is a cross-sectional view of the semiconductor substrateof FIG. 2e showing the etching of the poly-2 not covered by aphotoresist layer according to this invention.

[0028]FIG. 3f is a cross-sectional view of the semiconductor substrateof FIG. 2f showing the ion implanting of the SAS according to thisinvention.

[0029]FIG. 3g is a cross-sectional view of the semiconductor substrateof FIG. 2g showing the forming of the drain of the memory cell of thisinvention.

[0030]FIGS. 3h and 3 i show, respectively, the erasing and writingoperations of the disclosed split-gate flash memory cell represented bythe cross-sectional view taken at the 3 h-3 h location shown in FIG. 2h.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Referring now to the drawings, specifically to FIGS. 2a-2 h, andFIGS. 3a-3 i, there is shown a method of forming a split gate flashmemory cell having both a self-aligned source as well a floating gateself-aligned to a control gate. FIGS. 2a-2 h show plan views of asemiconductor substrate at different stages of the disclosed processingsteps. FIGS. 3a-3 i, on the other hand, show cross-sectional views ofthe substrate corresponding to locations shown on FIGS. 2a-2 h. FIGS. 3hand 3 i show the writing (programming) and erasing operations of thedisclosed memory cell represented by the cross-sectional view taken atthe 3 h-3 h location shown in FIG. 2h.

[0032] In FIG. 2a, substrate (100), preferably silicon, is provided withfield regions (103), and active device regions (105) already formedusing the well known methods including the LOCOS (local oxidation ofsilicon) method or the STI (shallow trench isolation) method. A firstgate oxide layer (120) is next grown thermally over the substrate at atemperature between about 850 to 950° C. to a thickness between about190 to 210 angstroms (Å). Alternatively, the gate oxide can be formed byan atmospheric or low pressure chemical vapor deposition (LPCVD) processas is well known. A cross-sectional view of the substrate including thefirst gate oxide layer is shown in FIG. 3a corresponding to the locationshown in FIG. 2a.

[0033] Next, a first polysilicon layer (poly-1) (130) (not shown as ablanket layer) is blanket deposited over the first gate oxide layer(120). This is accomplished through methods including but not limited toLow Pressure Chemical Vapor Deposition (LPCVD) methods, Chemical VaporDeposition (CVD) methods and Physical Vapor Deposition (PVD) sputteringmethods employing suitable silicon source materials, preferably formedthrough a LPCVD method employing silane SiH₄ as a silicon sourcematerial at a temperature range between about 550 to 620° C. Thepreferred thickness of the poly-1 layer is between about 900 to 1100angstroms (Å). It will be noted from FIG. 3b that gate oxide layer (120)serves the function of a control gate oxide here.

[0034] The poly-1 deposition is followed by the deposition of silicidelayer (140). As is known in the art, silicides can be formed by eitherdeposition of pure metal on silicon or co-evaporation of silicon andrefractory metal from two sources, or by sputter-depositing silicidefrom a composite target, or by co-sputtering or layering. The metal isusually selected from a refractory group consisting of tungsten,titanium, tantalum, molybdenum, and platinum and can either be depositedas a pure metal on a silicon bearing surface, or co-evaporated withsilicon. Here, it is preferred that layer (140) is formed byco-sputtering tungsten to a thickness between about 800 to 1500 Å.

[0035] A layer of oxide is then deposited over the substrate through thedecomposition of tetraethyl orthosilicate (TEOS) at a temperaturebetween about 600 to 650° C. Plasma Enhanced PECVD TEOS films can alsobe deposited at lower temperatures. It is preferred that thedecomposition temperature here is between about 300 to 400° C., and thatthe thickness of TEOS layer (150) is between about 1900 to 2100 Å.

[0036] A first photoresist layer, (not shown), is next formed andpatterned to define the control gate regions over the substrate. Usingthe patterned first photoresist layer as a photoresist mask, layers(150), (140) and (130) are then etched to form a vertical control gate(130) disposed below tungsten silicide (WSi_(x)) layer (140) and TEOSlayer (150) as shown in FIG. 3b. It will be noted from FIG. 3b that theetching is continued with high selectivity until silicon substrate isreached. Etching is accomplished in a HDP (high-density plasma) etcherwith etch recipe comprising gases O₂, HBr, Cl₂ and He to etch theWSi_(x) and Si, while CF₄, CHF₃ and O₂ gases are used to etch the TEOSlayer. For clarity, in the top view of the substrate shown in FIG. 2b,control gate (130) is shown without the overlying silicide and TEOSlayers. The layered structure is better seen in the cross-sectional viewin FIG. 3b.

[0037] Next, a second gate oxide layer, this time serving as a floatinggate oxide as well as an inter-gate or inter-poly oxide between controlgate (130) and the to-be-formed floating gate (170) shown in FIG. 3c isthermally grown to a thickness between about 70 to 90 Å at a temperaturebetween about 850 to 950° C. This is followed by forming a secondblanket polysilicon (poly-2) layer (not shown as a blanket layer in FIG.3c) preferably using the same LPCVD method as in forming the poly-1layer, with silane SiH₄ as a silicon source material at a temperaturerange between about 550 to 620° C. However, the blanket deposition ofpoly-2 is performed only to a partial depth, that is to the samethickness as the poly-1 layer of between about 1900 to 2100 Å so thatthe poly-2 layer does not reach to the height of the silicide layer northat of the TEOS layer. The so formed partial-depth poly-2 layer is thenetched anisotropically to form a spacer floating gate (170) as shown inFIG. 3c. A top view of spacer (170) can also be seen in FIG. 2c. It ispreferred that the etch recipe comprises O₂, HBr, Cl₂ and He.

[0038] It will be apparent to those skilled in the art that the methoddisclosed above enables the forming of the spacer floating gate (170)self-aligned to the vertical control gate (130), which is the mainfeature of this invention. Furthermore the etching forms a sharp peak ofpoly-2 (175) which is a key aspect for controlling the coupling ratiobetween the vertical control gate and the spacer floating gate of thisinvention, which in turn enhances the erasing function of the cell.

[0039] At the next step, a second photoresist layer (180) is formed overthe substrate as shown in both FIGS. 2d and 3 d and patterned to defineself-aligned source (SAS) region (109). Then etching is performedthrough the patterns in the second photoresist layer by using a dry etchrecipe comprising CF₄ , CHF₃ and O₂. It will be noted that this recipewill etch oxide only, and not silicon. However, it is important thatetching is carried out so that not all of the oxide in region (103) isremoved. It is preferred that an oxide layer with a thickness betweenabout 300 to 600 Å remains in regions (103) that are exposed to etchingas shown in FIGS. 2d and 2 e. The remaining oxide will serve as an etchstop when poly-2 spacer is next removed.

[0040] It will be appreciated by those skilled in the art that the sharppeak (175) of poly-2, that is, of the spacer floating gate (170), iswell protected during this step of SAS defining. Normally, the peak (43)of prior art shown in FIG. 1a, for example, would be damaged during theforming of source because it is not protected by a layer of photoresistand polysilicon, as is the case with the method disclosed here as shownin FIG. 3d. Thus, it is another key aspect of the present invention thatphotoresist and polysilicon are used as an etch-stop during the SAS etchwhich removes oxide only.

[0041] Second photoresist layer (180) is removed using oxygen plasmaashing after the defining of SAS region (109). Subsequently, a thirdphotoresist layer (190) is formed over the substrate and patterned asshown in both FIGS. 2e and 3 e. Of the two poly-2 spacers formedlaterally adjacent to one control gate, the one on thedrain-to-be-formed side of the cell is removed by etching through thepattern in the third photoresist layer shown in FIG. 3e. Etching isperformed with high selectivity to oxide using a recipe comprising O₂,HBr, Cl₂ and He. It will be noted that this etching removes poly-2 alsoover the STI regions not covered by the third photoresist layer.Further, the remaining 30 to 60 Å thick second gate oxide layer over theSAS region serves as an etch stop and protects the underlying siliconfrom damage during poly-2 etching.

[0042] A fourth photoresist layer (200) is next formed and patternedover the substrate as shown in FIG. 2f for redefining the self-alignedsource (109) shown in FIG. 3f. The SAS is next etched to removecompletely the remaining field, or isolation oxide in regions (103) overthe source area. This is followed by ion implanting (205) the SAS withphosphorous ions at a dosage level between about 1×10¹⁵ to −9×10¹⁵atoms/cm² and at an energy between about 10 to 60 KeV. Subsequently, thephotoresist layer is removed by oxygen plasma ashing. The source implantdiffusion is further increased during annealing of the tungsten silicideat a temperature between about 800 to 900° C., as shown in FIG. 3g.Drain (107) is next formed by ion implanting the drain region witharsenic ions at a dosage between about 1×10¹⁵ to 4×10¹⁵ atoms/cm² and atan energy between about 10 to 60 KeV. A top view of the substratecorresponding to these process steps are shown in FIGS. 2g and 2 h.

[0043] The forming of the split-gate flash memory cell according to thisinvention is completed by depositing an interlevel dielectric layer(ILD) to a thickness between about 10000 to 15000 Å, and opening contactholes and filling them with metal (not shown) following the presentstate of the art methods.

[0044] In FIG. 2h-a, programming operation of the disclosed split-gateflash memory cell is depicted where the source voltage V_(s) is set at 9volts, the drain voltage V_(d) at 1 volt, while the gate voltage V_(g)is set at 2 volts. Thus, electrons are transferred to the floating gate(170) as shown by the arrow (210) in the same FIG. 2h-a. For the erasingoperation shown in FIG. 2h-b, on the other hand, the source and drainvoltages are set at 0 volts, while the gate voltage at 11 volts. Underthis condition, the charge on the floating gate (170) tunnel through theintergate oxide layer (160) into control gate (130), thus reversing thestate of the floating gate of the memory cell. It will be noted that theenhanced sharp peak (175) of floating gate (170) improves electric fieldbetween the floating gate and the control gate and hence promotingfaster erase operation, while the spacer floating gate self-aligned tothe vertical control gate improves programmability, decreases thevariability of program, and the self-aligned source alleviatespunch-through from the source to drain.

[0045] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A method of forming split-gate flash memoryhaving a self-aligned source as well as a floating gate self-aligned tocontrol gate comprising the steps of: providing a silicon substratehaving a plurality of active and field regions defined by shallow trenchisolation (STI); forming first gate oxide layer over said substrate;forming first polysilicon (poly-1) layer over said first gate oxidelayer; forming silicide layer over said poly-1 layer; forming tetraethylorthosilicate (TEOS) layer over said silicide layer; forming firstphotoresist layer over said TEOS layer; patterning said firstphotoresist layer to define control gate area; etching said TEOS layerand said silicide layer through said patterning in said firstphotoresist layer and forming opening in said TEOS layer exposingportion of said poly-1 layer; etching said exposed portion of saidpoly-1 layer and forming control gate; removing said first photoresistlayer; forming second gate oxide layer over said substrate; formingpartial-depth second polysilicon (poly-2) layer over said second gateoxide layer; etching said partial-depth poly-2 layer to form drainspacer and source spacer and sharp peak therein; forming secondphotoresist layer over said substrate to define self-align source (SAS)region; etching partially said isolation oxide layer through said secondphotoresist layer in said SAS region; removing said second photoresistlayer; forming third photoresist layer over said substrate with openingsexposing said poly-2 drain spacer and said poly-2 covering said STIregions; etching through said openings in said third photoresist layerto remove said poly-2 drain spacer and said poly-2 covering said STIregions to form floating gate cell; forming fourth photoresist layerover said substrate to redefine self-align source (SAS) region; etchingcompletely said isolation oxide layer through said fourth photoresistlayer until said silicon substrate is reached in said SAS region; ionimplanting said SAS region; removing said fourth photoresist layer;annealing said tungsten silicide layer; forming drain in said substrate;forming interlevel dielectric layer (ILD) over said substrate; andforming metal contact in said ILD layer to complete the forming of saidsplit-gate flash memory cell.
 2. The method of claim 1 , wherein saidforming said first gate oxide layer is accomplished by thermal growth ata temperature between about 850 to 950° C.
 3. The method of claim 2 ,wherein said gate oxide layer has a thickness between about 190 to 210angstroms (Å).
 4. The method of claim 1 , wherein said forming a poly-1layer is accomplished with silicon source SiH₄ using LPCVD at atemperature between about 550 to 620° C.
 5. The method of claim 1 ,wherein said poly-1 layer has a thickness between about 900 to 1100angstroms (Å).
 6. The method of claim 1 , wherein said forming silicideis accomplished by co-sputtering tungsten.
 7. The method of claim 6 ,wherein the thickness of said silicide layer is between about 800 to1500 Å.
 8. The method of claim 1 , wherein said forming said TEOS layeris accomplished by decomposing tetraethyl orthosilicate at a temperaturebetween about 600-650° C.
 9. The method of claim 1 , wherein said TEOSlayer has a thickness between about 1900 to 2100 Å.
 10. The method ofclaim 1 , wherein said etching said TEOS layer is accomplished with etchrecipe comprising O₂ gas.
 11. The method of claim 1 , wherein saidetching said exposed portion of said poly-1 layer is accomplished with arecipe comprising gases HBr, Cl₂, He and O₂.
 12. The method of claim 1 ,wherein said forming said second gate oxide layer is accomplished bythermal growth at a temperature between about 850 to 950° C.
 13. Themethod of claim 1 , wherein said second oxide layer has a thicknessbetween about 70 to 90 Å.
 14. The method of claim 1 , wherein saidforming said partial-depth poly-2 layer is accomplished with siliconsource SiH₄ using LPCVD at a temperature between about 550 to 620° C.15. The method of claim 1 , wherein said partial-depth poly-2 layer hasa thickness between about 1900 to 2100 Å.
 16. The method of claim 1 ,wherein said etching said partial-depth poly-2 layer to form drainspacer and source spacer is accomplished with gases O₂, HBr, Cl₂ and He.17. The method of claim 1 , wherein said etching partially said secondgate oxide layer is accomplished with gases CF₄, CHF₃ and O₂.
 18. Themethod of claim 1 , wherein said etching partially said isolation oxidelayer is performed until said isolation oxide layer has a thicknessbetween about 300 to 600 Å.
 19. The method of claim 1 , wherein saidetching through said openings in said third photoresist layer to removesaid poly-2 drain spacer and said poly-2 covering said STI regions toform floating gate cell is accomplished with gases O₂, HBr, Cl₂ and He.20. The method of claim 1 , wherein said etching completely saidisolation oxide layer through fourth photoresist layer in said SASregion is accomplished with gases CF₄, CHF₃ and O₂.
 21. The method ofclaim 1 , wherein said ion implanting said SAS region is accomplished byimplanting phosphorous ions with a dosage between about 1×10¹⁵ to 9×10¹⁵atoms/cm² and at an energy between about 10 to 60 KeV.
 22. The method ofclaim 1 , wherein said annealing said silicide layer is accomplished ata temperature between about 800 to 900° C.
 23. The method of claim 1 ,wherein said forming said drain is accomplished by implanting arsenicions at a dosage level between about 1×10¹⁵ to 9×10¹⁵ atoms/cm² withenergy level between about 10 to 60 KeV.
 24. The method of claim 1 ,wherein said forming said interlevel ILD layer is accomplished bydepositing an oxide layer to a thickness between about 10,000 to 15,000Å.
 25. The method of claim 1 , wherein said forming said metal contactin said ILD layer is accomplished by patterning said ILD layer withcontact hole pattern and then filling with metal.
 26. A split-gate flashmemory cell with a self-aligned source and a floating gate self-alignedto control gate comprising: a substrate having active and field regionsdefined; a gate oxide formed over said substrate; a poly-1 layer forminga columnar control gate over said gate oxide; a silicide layer coveringsaid columnar control gate; a TEOS layer covering said silicide layer; apoly-2 layer forming a spacer floating gate adjacent and self-aligned tosaid columnar control gate with an intervening intergate oxide layer; asharp poly-2 peak in said spacer floating gate; and a self-alignedsource in said split-gate flash memory cell.
 27. The split-gate memorycell of claim 26 , wherein said gate oxide layer is formed by thermalgrowth at a temperature between about 850 to 950° C.
 28. The split-gatememory cell of claim 26 , wherein said poly-1 layer forming saidcolumnar control gate has a thickness between about 900 to 1100 Å. 29.The method of claim 26 , wherein said silicide layer is co-sputteredtungsten having a thickness between about 800 to 1500 Å.
 30. Thesplit-gate memory cell of claim 26 , wherein said TEOS layer hasthickness between about 1900 to 2100 Å.
 31. The split-gate memory cellof claim 26 , wherein said poly-2 layer forming said spacer floatinggate adjacent to said columnar control gate has a thickness betweenabout 1900 to 2100 Å.
 32. The split-gate memory cell of claim 26 ,wherein said intervening intergate oxide layer has a thickness betweenabout 70 to 90 Å.
 33. The split-gate memory cell of claim 26 , whereinsaid sharp poly-2 peak in said spacer floating gate has a thicknessbetween about 1900 to 2100 Å.